Electronic circuits, particularly logic circuits including microprocessors, are powered by at least one external power supply. When a power supply is initially turned on, the powered logic circuits must be initialized to a known state. Even after such circuitry has been initialized and is operating properly, the power supply voltage may for some reason dip or glitch unexpectedly, causing the logic circuitry to change state or otherwise operate improperly. It is therefore necessary to continuously monitor the power supply voltage and to reset the logic circuitry following such a glitch, after the power supply voltage reaches a predetermined minimum voltage adequate for proper operation. A reset operation, upon initial power-up or after a power supply glitch, is effected by a power-on reset logic signal. The present invention relates to monitoring power supply voltages and providing such a reset signal.
In the past, external reset circuits comprising discrete components have been utilized to provide a reset signal to an integrated circuit such as a microprocessor. Other types of voltage monitoring circuits have been used to monitor AC power lines. For example, international patent application no. PCT/US90/06301 owned by Voltage Control, Inc. discloses a discrete, analog circuit for monitoring an AC line voltage and disconnecting AC powered user equipment from the AC power line whenever the AC power line voltage is outside a predetermined operating voltage window. Use of discrete components is undesirable for most applications because of their large size and the cost of implementing discrete components.
Benhamida U.S. Pat. No. 5,109,163 discloses a power-on reset circuit which may be implemented as part of an integrated circuit chip including a microprocessor or other logic circuitry which may require initialization at powerup. U.S. Pat. No. 5,115,146 also shows an integrated power-on circuit. Monolithic power-on reset circuits are commercially available in bipolar technology. Examples of such devices are the TL7702 series of "supply voltage supervisors" made by Texas Instruments and the Fujitsu device number MV 3771.
Prior art power-on circuits provide for a timing capacitor (internal or external) to provide a delay period after a monitored power supply voltage is valid before asserting the reset signal. This assures that the power supply voltage has stabilized. Typically, the reset signal is derived from the capacitor node and is asserted when the capacitor is sufficiently charged. When the power supply voltage drops to an invalid level, a transistor switch discharges the timing capacitor. After the capacitor is sufficiently discharged, the reset signal changes to the invalid state. For example, the Fujitsu part No. MB 3771 employs an NPN transistor arranged to discharge an external timing capacitor (node C.sub.T) when the monitored voltage becomes invalid. The reset output signal is derived from that capacitor node so that, after the capacitor is sufficiently discharged, the reset output signal changes state. A similar approach is shown in Benhamida U.S. Pat. No. 5,109,163 (see FIG. 1, internal capacitor node C). In the prior art, switching the reset signal to the invalid state thus must await discharge of the timing capacitor. Discharging the timing capacitor introduces delay after the power supply voltage has dropped before asserting the reset signal. Such delay can lead to malfunction, particularly in high-speed systems. A need remains for asserting a reset signal to indicate an invalid power supply voltage without delay whenever the power supply voltage drops to an invalid level.
The prior art discrete and bipolar circuits are not amenable to implementation in CMOS technology. Moreover, both the circuits disclosed in the '163 patent (Benhamida) as well as the bipolar monolithic solutions suffer several common shortcomings. First, some prior art circuits employ input comparators with hysteresis. Hysteresis on the input has been found to be of little benefit. This is because, after an initial fault condition occurs, a relatively long delay period ensues during which the input is ignored. Additionally, hysteresis adds to the size and complexity of the comparators and makes it difficult to expand such reset circuits to monitor multiple power supply voltages.
The need remains, therefore, for an improved method of providing a power-on reset signal in a CMOS integrated system, and for circuitry for implementing such a method that is relatively simple and therefore compact in size. It would also be desirable to provide a power-on reset circuit which obviates providing hystersis in the input stage. The need also remains for providing an immediate indication of an invalid power supply voltage level.
Additionally, many integrated circuit systems require multiple power supply voltages. For example, a typical CMOS circuit may require both a +5 VDC supply (VDD) and a +12 VDC supply (VHH). It is therefore desirable to provide for monitoring multiple power supply voltages in a power-on reset circuit while minimizing circuit size and complexity.